The present invention relates to a low power phase locked loop (PLL) frequency synthesiser and to devices including the low power PLL frequency synthesiser. Such devices may comprise telemetry modules, computer peripherals including set top boxes, wireless mouse and wireless joystick and integrated circuits therefor.
An operating requirement for such devices is that they have a very short time frame, for example, 13.5 ms in the case of video games and the on/off ratio can be such that the time between transmissions is less than the ramp-up period. Consequently it is difficult to apply current economy.
An object of the present invention is to effect current economy in a low power radio system without having any effect on its performance.
According to a first aspect of the present invention there is provided a method of operating a phase locked loop(PLL) frequency synthesiser in which a voltage controlled oscillator(VCO) generates an output frequency, comprising determining when the PLL has stabilised, interrupting the PLL and de-energising at least those components used for determining the value of the control voltage supplied to the VCO, applying a locally produced control voltage to the VCO, periodically restoring the power to said de-energised components and restoring the PLL, and repeating the cycle after the PLL has stabilised.
According to a second aspect of the present invention there is provided a phase locked loop(PLL) frequency synthesiser comprising a reference oscillator, a first frequency determining means coupled to an output of the reference oscillator, a voltage controlled oscillator(VCO) having a control input and an output, a second frequency determining means coupled to the output of the VCO, phase comparing means coupled to outputs of the first and second frequency determining means, integrating means coupling an output of the phase comparing means to the control input of the VCO, switching means in the circuit path from the phase comparing means to the integrating means, said switching means when conductive completing the PLL but when non-conductive interrupting the PLL, voltage storing means for applying a control voltage to the control input of the VCO when the PLL is interrupted, control means for providing control signals for switching-off the reference oscillator and the first and second frequency determining means and for rendering the switching means non-conductive to interrupt the PLL, the VCO producing an output signal in accordance with the voltage provided by the voltage storage means, and further control signals for switching-on the reference oscillator and the first and second frequency determining means, for resetting the first and second frequency determining means and for rendering the switching means conductive to restore the PLL.
The PLL frequency synthesiser made in accordance with the present invention is able to save current by allowing parts of the circuit to be intentionally switched-off without compromising the output frequency stability unduly because the control voltage to the VCO of the PLL is maintained substantially constant for a predetermined time.
U.S. Pat. No. 5,410,572 discloses a PLL frequency synthesiser circuit of generally conventional design which is applied to power control equipment. The circuit comprises a VCO generating an output frequency in response to a control voltage. The control voltage is determined by dividing down the output frequency in a frequency divider. The divided down frequency is compared with a reference frequency in a phase comparator. The output of the phase comparator is filtered to provide the control voltage for the VCO. In order to avoid the power control equipment being disabled due to loss of the reference frequency due to say a power cut, the reference signal is detected and if a loss is noted, the PLL is interrupted by a switch which connects a steady voltage to the control voltage input of the VCO. The steady voltage may comprise a battery or a capacitor which in normal operation has a charge corresponding to the current control voltage. This cited invention does not relate to a technique in which components of the PLL frequency synthesiser are switched off and on to maintain the output frequency constant whilst simultaneously saving current. Additionally the citedspecification does not consider the effect of the decay of the charge on the capacitor which will pull the VCO frequency causing a frequency jump when the reference frequency is restored.
According to a third aspect of the present invention there is provided a transceiver comprising a receiving stage and a source of local oscillator signals coupled to the receiving stage, said source comprising a phase locked loop(PLL) frequency synthesiser comprising a reference oscillator, a first frequency determining means coupled to an output of the reference oscillator, a voltage controlled oscillator(VCO) having a control input and an output, a second frequency determining means coupled to the output of the VCO, phase comparing means coupled to outputs of the first and second frequency determining means, integrating means coupling an output of the phase comparing means to the control input of the VCO, switching means in the circuit path from the phase comparing means to the integrating means, said switching means when conductive completing the PLL but when non-conductive interrupting the PLL, voltage storage means for applying a control voltage to the control input of the VCO when the PLL is interrupted, control means for providing control signals for switching-off the reference oscillator and the first and second frequency determining means and for rendering the switching means non-conductive to interrupt the PLL, the VCO producing an output signal in accordance with the voltage provided by the voltage storage means, and further control signals for switching-on the reference oscillator and the first and second frequency determining means, for resetting the first and second frequency determining means and for rendering the switching means conductive to restore the PLL.
According to a fourth aspect of the present invention there is provided a wireless remote control device comprising a transceiver including a receiving stage and a source of local oscillator signals coupled to the receiving stage, said source comprising a phase locked loop(PLL) frequency synthesiser comprising a reference oscillator, a first frequency determining means coupled to an output of the reference oscillator, a voltage controlled oscillator(VCO) having a control input and an output, a second frequency determining means coupled to the output of the VCO, phase comparing means coupled to outputs of the first and second frequency determining means, integrating means coupling an output of the phase comparing means to the control input of the VCO, switching means in the circuit path from the phase comparing means to the integrating means, said switching means when conductive completing the PLL but when non-conductive interrupting the PLL, voltage storage means for applying a control voltage to the control input of the VCO when the PLL is interrupted, control means for providing control signals for switching-off the reference oscillator and the first and second frequency determining means and for rendering the switching means non-conductive to interrupt the PLL, the VCO producing an output signal in accordance with the voltage provided by the voltage storage means, and further control signals for switching-on the reference oscillator and the first and second frequency determining means, for resetting the first and second frequency determining means and for rendering the switching means conductive to restore the PLL.
The method of controlling the PLL frequency synthesiser enables the radio remote control device, for example computer peripherals including set-top boxes, a wireless mouse and a wireless joystick, to have the capability of continuous operation but the battery economy benefits of power cycling.